In order to perform at-speed testing of integrated circuit chips, the longest timing path through the chip must be identified. Electronic Design Automation (EDA) tools are implemented to identify long timing paths within a given design. EDA tools that attempt to identify long timing paths are referred to as Static Timing Analysis (STA) tools. However, the actual longest path in a given design is often difficult to identify due to false paths that the STA tool reports as the longest. A path that is falsely identified as the longest path is typically a path that cannot be exercised functionally on the tester. Once a functionally exercisable long path has been identified, stimulus patterns can be generated. Stimulus patterns are generated manually or with EDA tools. Stimulus patterns are run on a tester to verify that a piece of silicon (i.e., a given chip design and fabrication) is capable of operating at the desired target frequency. There can be millions of false paths hiding the true functionally exercisable longest path. As a result, the process of identifying functionally exercisable long paths and eliminating false paths can be a time, labor, and cost intensive task.
It would be desirable to have a method and/or architecture for at-speed testing integrated circuit chips that (i) reduces chip development cost and time and (ii) identifies functionally defective chips, and/or (iii) does not mis-identify functionally acceptable chips.